1. Field of the Invention
The present invention relates to a method for manufacturing a non-volatile memory, and more particularly to a method for manufacturing a non-volatile memory having a transistor using self-aligned offset source/drain.
2. Description of the Related Art
Proposals have been made on non-volatile memories in which an offset region is formed between a gate electrode and one of source/drain regions and another source/drain region is formed in self-alignment with respect to the gate electrode.
For example, Japanese Published Unexamined Patent Application No. HEI 4-14880 describes a method for forming a non-volatile memory which has a self-aligned offset region. The method for manufacturing one of such non-volatile memories will be detailed with reference to FIG. 15.
First, an oxide film 42 is formed on a P-type silicon substrate 41, and then, a polysilicon is deposited thereon and patterned into a desired configuration with the result that a first gate electrode 43 is formed. After one side of the first electrode 43 is covered with a resist (not shown in the drawing), N-type impurity ions are implanted using the first gate electrode 43 and the resist as a mask to form a lightly doped impurity diffusion layer 48. Then, after an oxide film 44 is formed on the silicon substrate 41 including the first gate electrode 43, a polysilicon is further deposited thereon. This polysilicon is etched with an anisotropic etching to form a polysilicon-made side wall spacer 45 on the side wall of the first gate electrode 43.
Then, this side wall spacer 45 serves as a mask for the ion implantation of N-type impurity ions 46. The substrate 41 thus implanted with N-type impurity ions 46 is subjected to heat treatment to form a diffusion layer 47. Thereafter, the side wall spacer 45 is removed by etching to form an oxide film on the first gate electrode 43, followed by forming a second gate electrode (not shown in the drawings).
In non-volatile memories formed by the above manufacturing method, the length of an offset region 49 can be determined by a region covered with the side wall spacer 45 with the result that the memory can be formed in self-alignment with respect to the end of the first gate electrode 43 and the memory can be well controlled and miniaturized.
However, the above method for manufacturing a non-volatile memory involves forming the gate oxide film below the first gate electrode 43 to a thickness 42 thinner than before along with the miniaturization of the cell area, which causes a problem that the silicon substrate 41 is likely to be damaged when the side wall spacer 45 is removed after ion implantation, and the thickness of the field oxide film becomes thinner, which decreases field inversion voltage. The above method further involves removing the polysil- icon-made side wall spacer 45 and then an insulation film that constitutes an etching stopper of the side wall spacer 45, and further forming a second gate oxide film again, which causes another problem that the number of manufacturing steps increases.